In a related art method of manufacturing transistors, a device isolation oxide layer and a source/drain region may be disposed in a silicon Si substrate, and may from a transistor structure. Accordingly, since the source/drain region may be disposed below the silicon substrate, it may be difficult to reduce a source/drain resistance.
Moreover, since a device isolation oxide layer may be formed by a shallow trench isolation (STI) process, transistor device characteristics may degrade due to an influence of stress caused by the STI process. In addition, a divot phenomenon, e.g., an abnormal hump phenomenon that may be caused by a wrap around phenomenon of a wafer, may occur and it may be difficult to control a leakage current caused by a STI edge.
A transistor device that may reduce a source/drain resistance and a leakage current to obtain device reliability may be beneficial.